Semiconductor memory device invalidating improper control command

ABSTRACT

A control circuit in a semiconductor memory device accessing a memory cell for a plurality of cycles includes an internal command generating circuit and a mask signal generating circuit. Upon receiving a control command, the internal command generating circuit outputs an internal signal instructing an operation to access the memory cell at H level when a mask signal is at L level, while outputs an internal signal at L level when the mask signal is at H level, because a latch circuit is reset. The mask signal generating circuit outputs the mask signal at H level for a following cycle, when the internal signal is output at H level.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,and more particularly to a semiconductor memory device whichcommunicates data with the outside in synchronization with a rise andfall of an external clock, and carries out a processing for access to amemory cell for a plurality of cycles with an operation at a higherfrequency.

[0003] 2. Description of the Background Art

[0004] With a demand for an operation with a higher frequency in thesemiconductor memory device, a double data rate SDRAM (hereinafter,referred to as a DDR SDRAM) communicating data with the outside insynchronization with rising and falling edges of an external clock hasbeen developed and put into practical use.

[0005] A first-generation DDR SDRAM referred to as a DDR-I performs a2-bit prefetch operation, in which 2-bit data received insynchronization with the successive rising and falling edges of theexternal clock is written at a time into a memory cell array for eachcycle, in each of a plurality of data input circuits (with regard todata read, the 2-bit data is read at a time from the memory cell arrayfor each cycle, corresponding to each of a plurality of data outputcircuits, and then, the 2-bit data is sequenced and output to theoutside every half cycle).

[0006] Recently, as a DDR SDRAM attaining an operation at a furtherhigher frequency, a second-generation DDR SDRAM referred to as a DDR-IIhas attracted attention. The DDR-II is standardized by “JEDEC” (JointElectron Device Engineering Council), which is an organizationstandardizing electronic devices in the United States.

[0007] The DDR-II is first characterized by a 4-bit prefetch operation.In the DDR-II, a time period itself from when execution of an internalprocessing is instructed until when memory cell is accessed is notdifferent from that in the DDR-I. Therefore, the processing for accessto the memory cell is not completed within one cycle, because anoperation frequency (an external clock frequency) is higher in theDDR-II. Accordingly, in the DDR-II, two cycles serve as one operationunit for the internal processing, and the memory cell is accessed foreach operation unit.

[0008] A write operation will be described as an example. In each of thedata input circuits, data of four bits received in synchronization withthe rising and falling edges of the external clock during consecutivetwo cycles is written at a time into the memory cell array every twocycles. In this manner, in the DDR-II, a data transfer rate within thedevice is doubled, compared to the DDR-I performing the 2-bit prefetchoperation, and thus, the operation frequency is enhanced.

[0009] Secondly, the DDR-II is characterized by using an additivelatency (hereinafter, also referred to as “AL”), a read latency(hereinafter, also referred to as “RL”), and a write latency(hereinafter, also referred to as “WL”) as a technique to improveoperation efficiency of a system having the semiconductor memory devicemounted. In the DRAM including the DDR SDRAM, a time period from when anactivation command (ACT command) is received until when a read commandor a write command (hereinafter, also collectively referred to as“column command”) is received is defined by a delay time tRCD as anoperation specification. When viewed from the system, however, from theviewpoint of the operation efficiency, it is desirable to be able toimmediately issue the column command in a following cycle after theissue of the ACT command. Therefore, in the DDR-II, the column commandwill be acceptable in a cycle following the reception of the ACTcommand, and the column command is delayed by the number of cyclesdefined with AL within the device, to secure time tRCD.

[0010] In addition, RL represents the number of cycles defined with(AL+CL), and represents the number of cycles from when the DDR-IIreceives the read command from the outside until when the DDR-II startsto output data to the outside. WL represents the number of cyclesdefined with (RL−1), and represents the number of cycles from when theDDR-I receives the write command from the outside until when the datawrite operation is started.

[0011] In doing so, from a viewpoint of the system having the DDR-IImounted, the column command can successively be issued after the ACTcommand, without taking into account delay time tRCD. That is, anefficient program can be set up.

[0012] As described above, in the DDR-II, two cycles of the externalclock serve as one operation unit. Therefore, the system utilizing theDDR-II is defined so as to issue a column command at an interval of atleast two cycles, during which an issue of a precharge command (PREcommand) is prohibited.

[0013] On the other hand, a command decoder used in a conventional DRAMincluding the DDR-I generates an internal control command correspondingto a control command received from the outside as it is, in response tothe control command. Therefore, when the control command is input everycycle, the command decoder generates the internal control command everycycle.

[0014] In such a case, when the conventional command decoder is used inthe DDR-II, and if the DDR-II receives an improper column command issuedin subsequent cycle, for example, the processing for access to thememory cell will overlap within one operation unit, and the data in thememory cell will be destroyed.

[0015] In addition, the internal control commands corresponding to aplurality of control commands the system issued at different timings maysimultaneously be generated within the DDR-II with AL and WL. Forexample, in the DDR-II, the internal control command corresponding tothe read command is generated after the number of cycles defined by AL,after the read command is received. Meanwhile, the internal controlcommand corresponding to the write command is generated after the numberof cycles defined by WL, after the write command is received. Therefore,when the DDR-II receives the read command after the write command, bothinternal control commands may be generated simultaneously. Further, theinternal control command corresponding to the read command receivedlater may be generated before the internal control command correspondingto the preceding write command is generated.

[0016] In such a case as well, as in the example in which the columncommands are input in consecutive cycles, the processing for access tothe memory cell may overlap within one operation unit, and the data inthe memory cell may be destroyed.

SUMMARY OF THE INVENTION

[0017] The present invention was made to solve the above-describedproblems. An object of the present invention is to provide asemiconductor memory device preventing data destruction even if animproper control command is input.

[0018] According to the present invention, a semiconductor memory devicecommunicates data with the outside in synchronization with a rise andfall of an external clock. The semiconductor memory device includes aplurality of memory cells storing data, an internal circuitinputting/outputting data to/from the plurality of memory cells, and acontrol circuit controlling an operation of the internal circuit in anoperation unit which is consecutive, multiple cycles of the externalclock as an operation unit. The control circuit includes an internalcommand generating circuit generating an internal control commandinstructing the operation of the internal circuit based on an externallyinput control command. The internal command generating circuit carriesout either first or second processing when it receives a plurality ofcontrol commands corresponding to a plurality of internal controlcommands generated in multiple cycles. In the first processing, aninternal control command corresponding to any one of the plurality ofcontrol commands is generated, while at least one, other control commandis invalidated. In the second processing, the plurality of controlcommands are all invalidated.

[0019] Therefore, according to the semiconductor memory device of thepresent invention, an improper control command that may cause anoverlapped access to a memory cell array is invalidated. Thus,destruction of stored data by such an improper command can be avoided.

[0020] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is an overall block diagram schematically showing aconfiguration of a semiconductor memory device according to the presentinvention.

[0022]FIG. 2 is an operational waveform diagram conceptuallyillustrating an operation of a control circuit in a semiconductor memorydevice in Embodiment 1.

[0023]FIG. 3 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in the controlcircuit in the semiconductor memory device according to Embodiment 1.

[0024]FIG. 4 is a circuit diagram showing a configuration of a latchcircuit shown in FIG. 3.

[0025]FIG. 5 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 3.

[0026]FIG. 6 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 2.

[0027]FIG. 7 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 6.

[0028]FIG. 8 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 3.

[0029]FIG. 9 is a circuit diagram showing a configuration of a delayelement shown in FIG. 8.

[0030]FIGS. 10 and 11 are circuit diagrams showing other configurationsof a delay element shown in FIG. 8.

[0031]FIG. 12 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 8.

[0032]FIG. 13 is an operational waveform diagram conceptuallyillustrating an operation of a control circuit in a semiconductor memorydevice in Embodiment 4.

[0033]FIG. 14 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in the controlcircuit in the semiconductor memory device according to Embodiment 4.

[0034]FIG. 15 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 14.

[0035]FIG. 16 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 5.

[0036]FIG. 17 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 16.

[0037]FIG. 18 is an operational waveform diagram conceptuallyillustrating an operation at a low frequency of a control circuit in asemiconductor memory device in Embodiment 6.

[0038]FIG. 19 is an operational waveform diagram conceptuallyillustrating an operation at a high frequency of the control circuit inthe semiconductor memory device in Embodiment 6.

[0039]FIG. 20 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in the controlcircuit in the semiconductor memory device according to Embodiment 6.

[0040]FIG. 21 is an operational waveform diagram illustrating anoperation at a low frequency of the control circuit shown in FIG. 20.

[0041]FIG. 22 is an operational waveform diagram illustrating anoperation at a high frequency of the control circuit shown in FIG. 20.

[0042]FIG. 23 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 7.

[0043]FIG. 24 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 23.

[0044]FIG. 25 is an operational waveform diagram conceptuallyillustrating an operation of a control circuit in a semiconductor memorydevice in Embodiment 8.

[0045]FIG. 26 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in the controlcircuit in the semiconductor memory device according to Embodiment 8.

[0046]FIG. 27 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 26.

[0047]FIG. 28 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 9.

[0048]FIG. 29 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 28.

[0049]FIG. 30 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 10.

[0050]FIG. 31 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 30.

[0051]FIG. 32 is an operational waveform diagram conceptuallyillustrating an operation of a control circuit in a semiconductor memorydevice in Embodiment 11.

[0052]FIG. 33 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in the controlcircuit in the semiconductor memory device according to Embodiment 11.

[0053]FIG. 34 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 33.

[0054]FIG. 35 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 12.

[0055]FIG. 36 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 35.

[0056]FIG. 37 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 13.

[0057]FIG. 38 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 37.

[0058]FIG. 39 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuitin a semiconductor memory device according to Embodiment 14.

[0059]FIG. 40 is an operational waveform diagram illustrating anoperation of the control circuit shown in FIG. 39.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] In the following, embodiments of the present invention will bedescribed in detail with reference to the figures. It is noted that thesame reference characters refer to the same or corresponding componentsin the figures, and description thereof will not be repeated.

[0061] (Embodiment 1)

[0062]FIG. 1 is an overall block diagram schematically showing aconfiguration of the semiconductor memory device according to thepresent invention.

[0063] Referring to FIG. 1, a semiconductor memory device 10 includes aclock terminal 12, a control signal terminal 14, an address terminal 16,a data input/output terminal 18, and a data strobe signal input/outputterminal 20.

[0064] In addition, semiconductor memory device 10 includes a clockbuffer 22, a control signal buffer 24, an address buffer 26, an inputbuffer 28 and an output buffer 30 relating to data DQ0-DQn (n representsa bit width in the semiconductor memory device), as well as an inputbuffer 32 and an output buffer 34 relating to data strobe signals UDQS,LDQS.

[0065] Moreover, semiconductor memory device 10 includes a readamplifier & P/S (parallel/serial) conversion circuit 36, an S/P(serial/parallel) conversion circuit & write driver 38, a DQS generatingcircuit 40, and a DLL circuit 41.

[0066] Furthermore, semiconductor memory device 10 includes a controlcircuit 42, a row decoder 44, a column decoder 46, a preamplifier &write amplifier 48, a sense amplifier 50, and a memory cell array 52.

[0067] It is to be noted that only main portions relating to datainput/output of semiconductor memory device 10 are shown as arepresentative in FIG. 1.

[0068] Clock terminal 12 receives an external clock ext.CLK, an externalclock ext./CLK complementary thereto, and a clock enable signal CKE.Control signal terminal 14 receives command control signals, that is, achip select signal /CS, a row address strobe signal /RAS, a columnaddress strobe signal /CAS, a write enable signal /WE, and input/outputDQ mask signals UDM, LDM. Address terminal 16 receives address signalsA0-A12 and bank address signals BA0, BA1.

[0069] Clock buffer 22 generates an internal clock CLK upon receivingexternal clocks ext.CLK, ext./CLK and clock enable signal CKE for outputto control signal buffer 24, address buffer 26, and control circuit 42.Control signal buffer 24 takes in and latches chip select signal /CS,row address strobe signal /RAS, column address strobe signal /CAS, writeenable signal /WE, and input/output DQ mask signals UDM, LDM insynchronization with internal clock CLK received from clock buffer 22,and outputs each internal control signal corresponding to respectivesignals to control circuit 42. Address buffer 26 takes in and latchesaddress signals A0-A12 and bank address signals BA0, BA1 insynchronization with internal clock CLK received from clock buffer 22,to generate an internal address signal, and outputs the signal to rowdecoder 44 and column decoder 46.

[0070] Data input/output terminal 18 communicates data read and writtenin semiconductor memory device 10 with the outside. Data input/outputterminal 18 receives data DQ0-DQn from the outside in data write, whileoutputs the same to the outside in data read. Data strobe signalinput/output terminal 20 receives from the outside data strobe signalsUDQS, LDQS coinciding with, or synchronous with, a timing edge of dataDQ0-DQn received from the outside in data write. On the other hand, datastrobe signal input/output terminal 20 outputs to the outside datastrobe signals UDQS, LDQS coinciding with, or synchronous with, thetiming edge of data DQ0-DQn output to the outside in data read.

[0071] Input buffer 28 receives data DQ0-DQn received from the outsideby data input/output terminal 18, in synchronization with data strobesignals UDQS, LDQS received from the outside by input buffer 32 via datastrobe signal input/output terminal 20.

[0072] Output buffer 30 operates in synchronization with a DLL clockgenerated by DLL circuit 41, and outputs data DQ0-DQn to datainput/output terminal 18 every half cycle. Output buffer 34 operates insynchronization with the DLL clock along with output buffer 30outputting data DQ0-DQn, and outputs data strobe signals UDQS, LDQSgenerated by DQS generating circuit 40 to data strobe signalinput/output terminal 20.

[0073] Read amplifier & P/S conversion circuit 36 amplifies read datareceived from preamplifier & write amplifier 48 in data read, andsequences 4-bit data read at a time as each data DQi (i: 0-n), to outputthe data to output buffer 30. S/P conversion circuit & write driver 38,in data write, outputs each data DQi received from input buffer 28 byone bit every half cycle to preamplifier & write amplifier 48 in 4-bitparallel every two cycles.

[0074] Control circuit 42 generates the internal control command basedon the internal control signal received from control signal buffer 24.Here, control circuit 42 does not generate a corresponding internalcontrol command with respect to the internal control signal received ina cycle following the reception of the internal control signal. Then,control circuit 42 outputs the generated internal control command to rowdecoder 44, column decoder 46, and preamplifier & write amplifier 48, tocontrol the operation of each of these circuits. Thus, data DQ0-DQn iswritten/read to/from memory cell array 52. In addition, control circuit42 controls generation of the data strobe signal in DQS generatingcircuit 40 based on the internal control signal that has been taken in.

[0075] Memory cell array 52 storing data consists of four banks, each ofwhich is operable independently. Data is read and written via senseamplifier 50.

[0076] DLL circuit 41 generates the DLL clock shifted backward withrespect to the edge of the external clock by an appropriate time,considering each circuit operation and a delay in signal propagation, sothat data DQ0-DQn output from output buffer 30 is output within aprescribed timing difference from external clocks ext.CLK, ext./CLK anddata strobe signal DQS output from output buffer 34 respectively.

[0077] Semiconductor memory device 10 performs the 4-bit prefetchoperation. That is, in data write, semiconductor memory device 10 takesin n-bit data every half cycle in synchronization with a rise and fallof the data strobe signal, and writes into memory cell array 52, the 4×nbit data of four half-cycles (equivalent to two cycles) every twocycles.

[0078] In addition, in data read, 4×n bit data is read from memory cellarray 52 every two cycles, and output to the outside by n bits everyhalf cycle in synchronization with the rise and fall of the data strobesignal.

[0079]FIG. 2 is an operational waveform diagram conceptuallyillustrating an operation of control circuit 42 in semiconductor memorydevice 10 in Embodiment 1.

[0080] Referring to FIG. 2, when semiconductor memory device 10 receivesa command from the outside at time T1 in synchronization with externalclock ext.CLK, control circuit 42 outputs an internal circuit activationsignal at H (logic high) level, and an operation for access to memorycell array 52 is instructed.

[0081] At time T2 in the next cycle, when semiconductor memory device 10receives a command from the outside, control circuit 42 outputs theinternal circuit activation signal corresponding to the command at L(logic low) level. In other words, the command input from the outside attime T2 is invalidated by control circuit 42. This is because the accessto memory cell array 52 will overlap, and because data will be destroyedwhen the internal circuit activation signals are activated inconsecutive cycles, as described above.

[0082] At time T3 in the next cycle, when semiconductor memory device 10further receives a command from the outside, control circuit 42 in turnoutputs the internal circuit activation signal corresponding to thecommand at H level. This is because the internal circuit activationsignal has not been activated at time T2 in the previous cycle, andbecause the access to memory cell array 52 will not overlap. A status attime T4 is similar to that at time T2.

[0083]FIG. 3 is a circuit diagram showing a configuration of a portioninvolved in generating the internal control command in control circuit42 in semiconductor memory device 10 according to Embodiment 1. Here,though a circuit relating to a write command is shown as arepresentative in FIG. 3, a similar circuit is provided for a readcommand as well.

[0084] Referring to FIG. 3, control circuit 42 includes an internalcommand generating circuit 102 and a mask signal generating circuit 104.Internal command generating circuit 102 includes an NAND gate G1, latchcircuits G3, G4, and inverters G7-G9. Mask signal generating circuit 104includes an NAND gate G2, latch circuits G5, G6, and an inverter G10.

[0085] NAND gate G1 calculates logical multiplication of internalcontrol signals CS, /RAS, CAS, WE received from control signal buffer42, and outputs a signal obtained by inverting the calculation result.Inverter G8 outputs a signal C1 obtained by inverting an output signalfrom NAND gate G1.

[0086] Inverter G7 outputs an internal clock /CLK obtained by invertinginternal clock CLK. Inverter G9 outputs an inverted signal of aninternal signal /POR. Here, internal signal /POR is an inverted signalof a power-on-reset signal POR.

[0087] Latch circuit G3 receives internal clock /CLK at a clock input.When internal clock /CLK is at H level, latch circuit G3 takes in signalC1 and outputs the signal as a signal C2. When internal clock /CLKattains L level, latch circuit G3 holds the taken-in signal C1, andoutputs the held signal as signal C2. In addition, latch circuit G3receives an output signal from inverter G9 at a reset input, and resetsthe held data when the reset input attains H level.

[0088] Latch circuit G4 receives internal clock CLK at a clock input.When internal clock CLK is at H level, latch circuit G4 takes in signalC2 and outputs the signal as a signal INTCOM. When internal clock CLKattains L level, latch circuit G4 holds the taken-in signal C2, andoutputs the held signal as signal INTCOM. In addition, latch circuit G4receives a mask signal Cmask described below at a reset input, andresets the held data when mask signal Cmask attains H level.

[0089] Here, signal INTCOM output from latch circuit G4 corresponds tothe internal control command, and attainment of H level of signal INTCOMcorresponds to generation of the internal control command.

[0090] Internal command generating circuit 102 operates insynchronization with internal clock CLK, and outputs signal INTCOM basedon internal control signals CS, /RAS, CAS, WE when mask signal Cmaskreceived from mask signal generating circuit 104 is at L level.Meanwhile, internal command generating circuit 102 outputs signal INTCOMat L level because latch circuit G4 is reset when mask signal Cmaskattains H level.

[0091] Latch circuit G5 receives internal clock /CLK at a clock input.When internal clock /CLK is at H level, latch circuit G5 takes in signalINTCOM and outputs the signal to latch circuit G6. When internal clock/CLK attains L level, latch circuit G5 holds the taken-in signal INTCOM,and outputs the held signal to latch circuit G6. In addition, latchcircuit G5 receives the output signal from inverter G9 at a reset input,and resets the held data when the reset input attains H level.

[0092] Latch circuit G6 receives internal clock CLK at a clock input.When internal clock CLK is at H level, latch circuit G6 takes in anoutput signal from latch circuit G5 and outputs the signal to inverterG1. When internal clock CLK attains L level, latch circuit G6 holds thetaken-in signal, and outputs the held signal to inverter G10. Inaddition, latch circuit G6 receives the output signal from inverter G9at a reset input, and resets the held data when the reset input attainsH level.

[0093] Inverter G10 outputs an inverted signal of an output signal fromlatch circuit G6. NAND gate G2 calculates logical multiplication of anoutput signal from inverter G10 and signal /POR, and outputs a signalobtained by inverting the calculation result as mask signal Cmask.

[0094] Mask signal generating circuit 104 outputs mask signal Cmask at Hlevel in a cycle following the output of signal INTCOM at H level byinternal command generating circuit 102, that is, the generation of theinternal control command. Thus, latch circuit G4 in internal commandgenerating circuit 102 is reset, and signal INTCOM is output at L levelduring that cycle. In other words, the internal control command is notgenerated in a cycle following the generation of the internal controlcommand.

[0095] It is to be noted that mask signal generating circuit 104 insemiconductor memory device 10 according to Embodiment 1 constitutes a“signal generating circuit.”

[0096]FIG. 4 is a circuit diagram showing a configuration of latchcircuits G3-G6 shown in FIG. 3.

[0097] Referring to FIG. 4, each of latch circuits G3-G6 includes an NORgate G11, and inverters G12-G14. Inverter G12 outputs an inverted signalof a clock input Clock. Inverter G13 is activated when an output signalof inverter G12 is at L level, and outputs an inverted signal of aninput signal in. NOR gate G11 calculates logical sum of an output signalfrom inverter G13 and a reset input Reset, and inverts the calculationresult to output an output signal out. Inverter G14 is activated whenclock input Clock is at L level, and outputs an inverted signal ofoutput signal out to an output node of inverter G13.

[0098] NOR gate G11 and inverter G14 attain a latch function while clockinput Clock maintains L level when reset input Reset is at L level.

[0099]FIG. 5 is an operational waveform diagram illustrating anoperation of control circuit 42 shown in FIG. 3.

[0100] Referring to FIG. 5, when a write command is externally input attime T1, signals C1 and C2 attain H level. When external clock ext.CLKrises at time T2, internal command generating circuit 102 outputs signalINTCOM at H level.

[0101] When the command is reset and signal C1 attains L level at timeT3, and when external clock ext.CLK falls at time T4, signal C2 attainsL level while signal INTCOM is maintained at H level by latch circuitG4.

[0102] When the write command is input again from the outside at timeT5, and when external clock ext.CLK rises at time T6, mask signalgenerating circuit 104 outputs mask signal Cmask at H level becausesignal INTCOM has attained H level at time T4. Therefore, latch circuitG4 in internal command generating circuit 102 is reset, and signalINTCOM attains L level. In other words, control circuit 42 invalidatesthe command received in succession at time T5 after the command receivedat time T1, and does not generate a corresponding internal controlcommand.

[0103] When the write command is externally input again at time T9, andwhen external clock ext.CLK rises at time T10, mask signal generatingcircuit 104 outputs mask signal Cmask at L level because signal INTCOMhas attained L level at time T8. Therefore, reset of latch circuit G4 iscanceled, signal INTCOM attains H level in response to the input writecommand, and control circuit 42 generates a corresponding internalcontrol command.

[0104] In the above description, semiconductor memory device 10 performsthe 4-bit prefetch operation in which the processing for access to thememory cell array is carried out, spanning over two cycles. Thesemiconductor memory device, however, can readily be expanded to asemiconductor memory device performing a 2×k bit prefetch operation (kis an integer larger than 2) further improving an internal data transferrate.

[0105] That is, in the semiconductor memory device performing the 2×k(k>2) bit prefetch operation, in order to invalidate a command receivedduring (k−1) cycles starting from a cycle following the reception of acommand from the outside, following conditions are necessary. That is,2×(k−1) latch circuits connected in series constitute the mask signalgenerating circuit; a signal obtained by shifting signal INTCOM by 1 to(k−1) cycles is generated; and a signal obtained from logical sum ofeach signal is employed as mask signal Cmask.

[0106] In addition, in the above description, mask signal Cmaskgenerated by mask signal generating circuit 104 has been used for asignal for resetting latch circuit G4. Instead of mask signal Cmask,however, a control signal for the memory cell array having a comparablesignal timing can be used, for example. This will eliminate a need toprovide mask signal generating circuit 104.

[0107] As described above, according to semiconductor memory device 10in Embodiment 1, a command received in a cycle following the receptionof a command is invalidated. Therefore, an overlapped access to thememory cell array by a plurality of commands is prevented, and datadestruction is avoided.

[0108] (Embodiment 2)

[0109] In semiconductor memory device 10 in Embodiment 1, latch circuitG4 in internal command generating circuit 102 has been reset by masksignal Cmask generated by mask signal generating circuit 104, and thus,an improper control command has been invalidated. In a semiconductormemory device 10A in Embodiment 2, with respect to the improper controlcommand, an output of the internal command generating circuit is blockedby using a mask signal generated by the mask signal generating circuit.

[0110] Semiconductor memory device 10A in Embodiment 2 includes acontrol circuit 42A instead of control circuit 42 in the configurationof semiconductor memory device 10 shown in FIG. 1. Since otherconfigurations are the same, description thereof will not be repeated.

[0111]FIG. 6 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42A in semiconductor memory device 10A according to Embodiment 2. InFIG. 6 as well, a circuit relating to the write command is shown as arepresentative, as in FIG. 3.

[0112] Referring to FIG. 6, control circuit 42A includes an internalcommand generating circuit 102A and a mask signal generating circuit104A. Internal command generating circuit 102A further includes an ANDgate G15 in the configuration of internal command generating circuit 102in Embodiment 1, and receives the output signal from inverter G9 insteadof mask signal Cmask at a reset input of latch circuit G4. Mask signalgenerating circuit 104A includes an NOR gate G16 instead of NAND gate G2in the configuration of mask signal generating circuit 104 in Embodiment1.

[0113] AND gate G15 calculates logical multiplication of an outputsignal C3 from latch circuit G4 and mask signal /Cmask which is anoutput signal from mask signal generating circuit 104A, and outputs thecalculation result as signal INTCOM. NOR gate G16 calculates logical sumof output signals from latch circuit G6 and inverter G10, and outputs asignal obtained by inverting the calculation result as mask signal/Cmask.

[0114] Internal command generating circuit 102A outputs signal INTCOMbased on internal control signals CS, /RAS, CAS, WE when mask signal/Cmask received from mask signal generating circuit 104 is at H level.Meanwhile, when mask signal /Cmask is at L level, an output signal ofAND gate G15 is fixed to L level. Therefore, internal command generatingcircuit 102A outputs signal INTCOM at L level. In other words,generation of the internal control command is blocked.

[0115] When internal command generating circuit 102A outputs signalINTCOM at H level, mask signal generating circuit 104A outputs masksignal /Cmask at L level in a following cycle.

[0116]FIG. 7 is an operational waveform diagram illustrating anoperation of control circuit 42A shown in FIG. 6.

[0117] Referring to FIG. 7, when the write command is externally inputat time T1, and when external clock ext.CLK rises at time T2, latchcircuit G4 outputs signal C3 at H level. Since mask signal /Cmaskattains H level at this time point, internal command generating circuit102A outputs signal INTCOM at H level in accordance with signal C3.

[0118] When the write command is externally input again at time T5, andwhen external clock ext.CLK rises at time T6, mask signal generatingcircuit 104A outputs mask signal /Cmask at L level because signal INTCOMhas attained H level at time T4. Then, the output signal of AND gate G15in internal command generating circuit 102 is fixed to L level, andsignal INTCOM attains L level. In other words, a command received insuccession at time T5 after the command received at time T1 isinvalidated, and generation of a corresponding internal control commandis blocked.

[0119] When the write command is externally input again at time T9, andwhen external clock ext.CLK rises at time T10, mask signal generatingcircuit 104A outputs mask signal /Cmask at H level because signal INTCOMhas attained L level at time T8. Therefore, signal INTCOM attains Hlevel in accordance with signal C3, and an internal control commandcorresponding to the command received at time T9 is generated.

[0120] Here, semiconductor memory device 10A according to Embodiment 2is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 according to Embodiment 1.

[0121] In addition, as described in Embodiment 1, instead of mask signalCmask generated by a mask signal generating circuit 104A, a controlsignal of the memory cell array having a comparable signal timing may beused, for example.

[0122] As described above, according to semiconductor memory device 10Ain Embodiment 2 as well, an overlapped access to the memory cell arrayby a plurality of commands is blocked, and data destruction can beavoided, as in semiconductor memory device 10 in Embodiment 1.

[0123] (Embodiment 3)

[0124] In a semiconductor memory device 10B according to Embodiment 3,an input of an improper control command to the internal commandgenerating circuit is blocked by a use of the mask signal generated bythe mask signal generating circuit.

[0125] Semiconductor memory device 10B according to Embodiment 3includes a control circuit 42B instead of control circuit 42 in theconfiguration of semiconductor memory device 10 shown in FIG. 1. Sinceother configurations are the same, description thereof will not berepeated.

[0126]FIG. 8 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42B in semiconductor memory device 10B according to Embodiment 3. Here,as in FIG. 3, a circuit relating to the write command is shown as therepresentative also in FIG. 8.

[0127] Referring to FIG. 8, control circuit 42B includes an internalcommand generating circuit 102B and a mask signal generating circuit104B. In the configuration of internal command generating circuit 102 inEmbodiment 1, internal command generating circuit 102B does not includeinverter G8 but further includes an NOR gate G21 between latch circuitsG3 and G4. In addition, internal command generating circuit 102Breceives the output signal from inverter G9 instead of mask signal Cmaskat the reset input of latch circuit G4. Mask signal generating circuit104B includes latch circuit G5 and a delay element G20.

[0128] NOR gate G21 calculates logical sum of signal C2 output fromlatch circuit G3 and mask signal Cmask which is an output signal fromdelay element G20 in mask signal generating circuit 104B, and outputs asignal obtained by inverting the calculation result as signal C3. Latchcircuit G4 receives signal C3 at the input, and outputs signal INTCOM.

[0129] Delay element G20 delays a signal received from latch circuit G5by a prescribed time, and outputs mask signal Cmask. Delay element G20is provided in order to completely mask signal INTCOM. Details thereofwill be discussed later in description for the operational waveform ofcontrol circuit 42B.

[0130]FIG. 9 is a circuit diagram showing a configuration of delayelement G20 shown in FIG. 8. Referring to FIG. 9, delay element G20includes inverters G22-G25 connected in series. It is to be noted thatthe number of inverters is appropriately adjusted in accordance with adesired delay time.

[0131]FIG. 10 is a circuit diagram showing another configuration ofdelay element G20 shown in FIG. 8. Referring to FIG. 10, delay elementG20 includes inverters G26, G27, and capacitors C1, C2.

[0132]FIG. 11 is a circuit diagram showing another configuration ofdelay element G20 shown in FIG. 8. Referring to FIG. 11, delay elementG20 includes a resistance element R1.

[0133]FIG. 12 is an operational waveform diagram illustrating anoperation of control circuit 42B shown in FIG. 8.

[0134] Referring to FIG. 12, when the write command is externally inputat time T1, signals C1, C2 attain L level. In addition, as mask signalCmask is at L level, signal C3 attains H level. Therefore, when externalclock ext.CLK rises at time T2, internal command generating circuit 102Boutputs signal INTCOM at H level.

[0135] When the command is reset at time T3 and signal C1 attains Hlevel, and when external clock ext.CLK falls at time T4, signals C2, C3attain H level and L level respectively. At this timing, latch circuitG5 outputs a signal of H level, and delay element G20 delays the signaloutput from latch circuit G5 by a prescribed time, to output mask signalCmask at H level. Accordingly, signal C3 attains L level.

[0136] When the write command is externally input again at time T5, andwhen external clock ext.CLK rises at time T6, signal INTCOM attains Llevel because signal C3 has attained L level. Then, when signal C2attains H level in response to the fall of external clock ext.CLK attime T8, and when latch circuit G5 outputs a signal of L level, masksignal Cmask attains L level after a delay from time T8, produced bydelay element G20. In other words, since delay element G20 is provided,mask signal Cmask attains L level before signal C2 attains H levelthrough signal skew. Therefore, a possibility that signal INTCOMinadvertently attains H level is eliminated, and unintentionalgeneration of an internal control command is prevented.

[0137] When the write command is externally input again at time T9, andwhen signal C2 attains L level again, signal C3 attains H level becausemask signal Cmask has attained L level. Therefore, when external clockext.CLK rises at time T10, internal command generating circuit 102Boutputs signal INTCOM at H level, and a corresponding internal controlcommand is generated.

[0138] Here, semiconductor memory device 10B according to Embodiment 3is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 according to Embodiment 1.

[0139] In addition, instead of mask signal Cmask generated by masksignal generating circuit 102B, a control signal of the memory cellarray having a comparable signal timing may be used, for example, as asignal fixing an input of latch circuit G4 to L level, as described inEmbodiment 1.

[0140] As described above, according to semiconductor memory device 10Bin Embodiment 3 as well, an overlapped access to a memory cell array bya plurality of commands can be prevented, and data destruction can beavoided, as in semiconductor memory device 10 in Embodiment 1.

[0141] (Embodiment 4)

[0142] In Embodiments 1 to 3, a command in a cycle following thereception of a former command has been invalidated. In Embodiment 4, thecommand in the following cycle is regarded as valid, if the formercommand is canceled within that cycle in which that former command isreceived.

[0143] A semiconductor memory device 10C in Embodiment 4 includes acontrol circuit 42C instead of control circuit 42 in the configurationof semiconductor memory device 10 shown in FIG. 1. Since otherconfigurations are the same, description thereof will not be repeated.

[0144]FIG. 13 is an operational waveform diagram conceptuallyillustrating an operation of control circuit 42C in semiconductor memorydevice 10C in Embodiment 4.

[0145] Referring to FIG. 13, when semiconductor memory device 10Creceives a command from the outside at time T1 in synchronization withexternal clock ext.CLK, control circuit 42C outputs an internal circuitactivation signal at H level. Thereafter, when a cancel command is inputat time T2, control circuit 42C sets the internal circuit activationsignal to L level. Then, when a command is input again at time T3,control circuit 42C does not invalidate the command, even though thecommand is received in consecutive cycles, but outputs the correspondinginternal circuit activation signal at H level.

[0146] Next, when semiconductor memory device 10C receives a command attime T4 in the next cycle, control circuit 42C does not generate aninternal control command corresponding to that command. In other words,control circuit 42C invalidates the command received at time T4. Thereason is as follows. That is, when the internal circuit activationsignals are activated in the consecutive cycles, access to memory cellarray 52 overlaps, and data will be destroyed, as described before.

[0147]FIG. 14 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42C in semiconductor memory device 10C according to Embodiment 4. Here,as in FIG. 3, a circuit relating to the write command is shown as therepresentative also in FIG. 14.

[0148] Referring to FIG. 14, control circuit 42C includes internalcommand generating circuit 102, a mask signal generating circuit 104C,and a column activation signal generating circuit 106. Mask signalgenerating circuit 104C further includes an NAND gate G31 in theconfiguration of mask signal generating circuit 104 in Embodiment 1, andreceives an output signal from NAND gate G31 instead of the outputsignal from inverter G9 at the reset inputs of latch circuits G5, G6.Column activation signal generating circuit 106 includes NAND gatesG28-G30 and inverter G32. Here, description for the configuration ofinternal command generating circuit 102 has already been provided, andwill not be repeated.

[0149] NAND gate G31 calculates logical multiplication of an outputsignal from inverter G32 in column activation signal generating circuit106 and an internal signal /POR, and outputs a signal obtained byinverting the calculation result. NAND gate G28 calculates logicalmultiplication of internal clock CLK and signal INTCOM, and outputs asignal obtained by inverting the calculation result. NAND gate G29calculates logical multiplication of a cancel signal /CANSEL, a burstend signal /BL, internal signal /POR, and an output signal from NANDgate G30, and outputs a signal obtained by inverting the calculationresult.

[0150] Here, cancel signal /CANSEL serves to terminate activation of acolumn system, and attains L level corresponding to a cancel commandsuch as a PRE command or a termination command. Burst end signal /BLattains L level when a burst operation ends.

[0151] NAND gate G30 calculates logical multiplication of output signalsfrom NAND gates G28, G29, and outputs a signal obtained by inverting thecalculation result. Inverter G32 outputs an inverted signal of theoutput signal from NAND gate G29.

[0152] Column activation signal generating circuit 106 outputs a columnactivation signal COLACT at H level in response to attainment of H levelof signal INTCOM, and usually, sets column activation signal COLACT to Llevel in response to attainment of L level of burst end signal /BL. Onthe other hand, column activation signal generating circuit 106 setscolumn activation signal COLACT to L level also when cancel signal/CANSEL attains L level in response to the cancel command after columnactivation signal COLACT is output at H level.

[0153] When column activation signal COLACT is set to L level, latchcircuits G5 and G6 are reset, and then, mask signal generating circuit104C is inactivated. In other words, even if the command is externallyinput and internal command generating circuit 102 outputs signal INTCOMat H level, mask signal generating circuit 104C does not set mask signalCmask to H level in the next cycle, when the cancel command is input toterminate activation of the column system, and when column activationsignal COLACT attains L level. Therefore, control circuit 42C does notinvalidate a command input in a cycle following the reception of thecancel command, and internal command generating circuit 102 generates aninternal control command corresponding to that command.

[0154]FIG. 15 is an operational waveform diagram illustrating anoperation of control circuit 42C shown in FIG. 14.

[0155] Referring to FIG. 15, when the write command is input at time T1,and when external clock ext.CLK rises at time T2, internal commandgenerating circuit 102 outputs signal INTCOM at H level. Accordingly,column activation signal generating circuit 106 outputs columnactivation signal COLACT at H level.

[0156] When the cancel command is input and cancel signal /CANCELattains L level at time T3, column activation signal generating circuit106 sets column activation signal COLACT to L level. Then, mask signalgenerating circuit 104C is inactivated, and mask signal generatingcircuit 104C does not set mask signal Cmask to H level at time T7 in thenext cycle.

[0157] Therefore, internal command generating circuit 102 does notinvalidate the write command received at time T6, but outputs signalINTCOM at H level in response to the rise of external clock ext.CLK attime T7. Accordingly, column activation signal generating circuit 106also outputs column activation signal COLACT at H level.

[0158] When the write command is input at time T10 in the next cycle,and when external clock ext.CLK rises at time T11, mask signalgenerating circuit 104C in turn outputs mask signal Cmask at H level.Therefore, internal command generating circuit 102 outputs signal INTCOMat L level. In other words, internal command generating circuit 102invalidates the write command received at time T10.

[0159] Here, semiconductor memory device 10C according to Embodiment 4is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 according to Embodiment 1.

[0160] As described above, according to semiconductor memory device 10Cin Embodiment 4, if the cancel command is input within the cycle inwhich the command is received, a command received in a following cycleis regarded as valid, and an unnecessary command invalidating processingis avoided.

[0161] (Embodiment 5)

[0162] In Embodiments 1 to 3, when a command is input, a command in afollowing cycle has been invalidated. In those embodiments, a targetcommand has been column command. In Embodiment 4, a cancel command inputin a cycle following the input of a column command is also invalidated.Thus, if column commands are input in consecutive cycles, an overlappedaccess to the memory cell array is prevented. In addition, interruptionby a cancel command, of an effective processing for access to the memorycell array by a preceding command is prevented.

[0163] A semiconductor memory device 10D in Embodiment 5 includes acontrol circuit 42D instead of control circuit 42C in the configurationof semiconductor memory device 10C shown in FIG. 14. Since otherconfigurations are the same, description thereof will not be repeated.

[0164]FIG. 16 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42D in semiconductor memory device 10D according to Embodiment 5. Here,as in FIG. 3, a circuit relating to the write command is shown as therepresentative also in FIG. 16.

[0165] Referring to FIG. 16, control circuit 42D includes a columnactivation signal generating circuit 106A instead of column activationsignal generating circuit 106 in the configuration of control circuit42C in Embodiment 4. Column activation signal generating circuit 106Afurther includes an OR gate G33 in the configuration of columnactivation signal generating circuit 106, and an output signal from ORgate G33 instead of cancel signal /CANCEL is input to NAND gate G29.

[0166] OR gate G33 outputs a signal obtained by calculating logical sumof cancel signal /CANCEL and mask signal Cmask.

[0167] When mask signal Cmask generated by mask signal generatingcircuit 104C attains H level, column activation signal generatingcircuit 106A masks cancel signal /CANCEL and invalidates the cancelcommand input in a cycle following the input of the column command.

[0168]FIG. 17 is an operational waveform diagram illustrating anoperation of control circuit 42D shown in FIG. 16.

[0169] Referring to FIG. 17, after the write command is input at timeT1, the write command is input at time T5 in the next cycle. Whenexternal clock ext.CLK rises at time T6, mask signal Cmask attains Hlevel, and signal INTCOM attains L level. Here, when the cancel commandis input immediately after time T6, cancel signal /CANCEL attains Llevel. However, since mask signal Cmask is at H level, cancel signal/CANCEL is masked, and the cancel command is invalidated.

[0170] Here, semiconductor memory device 10D according to Embodiment 5is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 in Embodiment 1.

[0171] In addition, a control signal of the memory cell array having acomparable signal timing, for example, can be used as a signal resettinglatch circuit G4 and a signal masking cancel signal /CANCEL, asdescribed in Embodiment 1.

[0172] As described above, according to semiconductor memory device 10Din Embodiment 5, a cancel command received in a cycle following thereception of a command is also invalidated. Therefore, interruption bythe cancel command, of the effective processing for access to the memorycell array by the preceding command is prevented.

[0173] (Embodiment 6)

[0174] The semiconductor memory device described above can handle anoperation with a high frequency. When it is used for an operation with alow frequency, however, in a duration of one operation unit consistingof predetermined multiple cycles, access to the memory cell array iscompleted, leaving extra one or more cycles. Then, a waiting time forprocessing is produced until that operation unit expires.

[0175] Therefore, in Embodiment 6, an access monitoring circuit countinga time from when a command is input until when a processing for accessto the memory cell array is completed is provided. A command input in acycle following the completion of the processing for access to thememory cell array is regarded as valid.

[0176] A semiconductor memory device 10E in Embodiment 6 includes acontrol circuit 42E instead of control circuit 42 in the configurationof semiconductor memory device 10 shown in FIG. 1. Since otherconfigurations are the same, description thereof will not be repeated.

[0177]FIGS. 18 and 19 are operational waveform diagrams conceptuallyillustrating an operation of control circuit 42E in semiconductor memorydevice 42E in Embodiment 6. FIG. 18 shows an example in which anexternal clock has a low frequency, while FIG. 19 shows an example inwhich the external clock has a high frequency.

[0178] Referring to FIG. 18, when semiconductor memory device 10Ereceives a command from the outside at time T1 in synchronization withexternal clock ext.CLK, control circuit 42E outputs the internal circuitactivation signal at H level. The access monitoring circuit startscounting, and outputs a signal of H level.

[0179] As the external clock has a low frequency, the access monitoringcircuit sets the output signal to L level when the processing for accessto the memory cell array is completed at time T3 before time T4 in thenext cycle. Then, control circuit 42E does not invalidate a commandreceived in the next cycle, but the command input at time T4 iseffectively processed.

[0180] Referring to FIG. 19, when the external clock has a highfrequency, the processing for access to the memory cell arraycorresponding to the command input at time T1 is not completed at timeT3 in the next cycle. Control circuit 42E invalidates the commandreceived at time T3, and outputs the internal circuit activation signalat L level.

[0181] When the processing for access to the memory cell array iscompleted at time T5, the access monitoring circuit sets the outputsignal to L level. Therefore, control circuit 42E regards the commandreceived at time T6 as valid, and outputs the internal circuitactivation signal at H level.

[0182]FIG. 20 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42E in semiconductor memory device 10E according to Embodiment 6. Here,as in FIG. 3, a circuit relating to the write command is shown as therepresentative also in FIG. 20.

[0183] Referring to FIG. 20, control circuit 42E includes internalcommand generating circuit 102, a mask signal generating circuit 104D,and an access monitoring circuit 108. Mask signal generating circuit104D includes an NAND gate G44 instead of inverter G10 in theconfiguration of mask signal generating circuit 104 in Embodiment 1.Access monitoring circuit 108 includes delay elements G17, G18, NANDgates G35-G37, latch circuits G38, G39, and inverters G40-G43. Here,description for the configuration of internal command generating circuit102 has already been provided, and will not be repeated.

[0184] NAND gate G44 calculates logical multiplication of output signalsfrom latch circuits G6, G39, and outputs a signal obtained by invertingthe calculation result to NAND gate G2. Delay element G17 outputs asignal obtained by delaying signal INTCOM by a prescribed time. InverterG40 outputs an inverted signal of an output signal from delay elementG17. NAND gate G35 calculates logical multiplication of signal INTCOMand an output signal from inverter G40, and outputs a signal obtained byinverting the calculation result. A circuit group constituted with delayelement G17, inverter G40, and NAND gate G35 generates a falling pulsesignal having a pulse width of a delay time by delay element G17, inresponse to attainment of H level of signal INTCOM.

[0185] Delay element G18 receives a signal Colwidth, which is an outputsignal from NAND gate G36, and outputs a signal obtained by delayingsignal Colwidth, during a time period from when the command is inputuntil when the access to the memory cell array is completed. InverterG41 outputs an inverted signal of an output signal from delay elementG18. NAND gate G36 calculates logical multiplication of output signalsfrom NAND gates G35, G37, and outputs a signal obtained by inverting thecalculation result. NAND gate G37 calculates logical multiplication ofoutput signals from inverter G41 and NAND gate G36, and outputs a signalobtained by inverting the calculation result.

[0186] Inverter G42 outputs internal clock /CLK obtained by invertinginternal clock CLK. Inverter G43 outputs an inverted signal of internalsignal /POR.

[0187] Latch circuit G38 receives internal dock /CLK at a clock input.When internal clock /CLK is at H level, latch circuit G38 takes in andoutputs signal Colwidth, and when internal clock /CLK attains L level,latch circuit G38 holds the taken-in signal Colwidth, and outputs theheld signal. In addition, latch circuit G38 receives an output signalfrom inverter G43 at a reset input, and resets the held data when thereset input attains H level.

[0188] Latch circuit G39 receives internal dock CLK at a clock input.When internal clock CLK is at H level, latch circuit G39 takes in anoutput signal from latch circuit G38, and outputs the signal as a signalCmaskEN. When internal clock CLK attains L level, latch circuit G39holds the taken-in signal, and outputs the held signal as signalCmaskEN. In addition, latch circuit G39 receives the output signal frominverter G43 at a reset input, and resets the held data when the resetinput attains H level.

[0189] It is to be noted that access monitoring circuit 108 insemiconductor memory device 10E according to Embodiment 6 constitutes“another signal generating circuit.”

[0190]FIGS. 21 and 22 are operational waveform diagrams conceptuallyillustrating an operation of control circuit 42E shown in FIG. 20. FIG.21 shows an example in which the external clock has a low frequency,while FIG. 22 shows an example in which the external clock has a highfrequency.

[0191] Referring to FIG. 21, when the write command is externally inputat time T1, and when external clock ext.CLK rises at time T2, internalcommand generating circuit 102 outputs signal INTCOM at H level.Accordingly, access monitoring circuit 108 outputs signal Colwidth at Hlevel.

[0192] In the example in which the external clock has a low frequency,at time T5 before the next cycle starts, when a delay time by delayelement G18 simulating an access time has passed, access monitoringcircuit 108 sets signal Colwidth to L level. Therefore, in this example,signal CmaskEN does not attain H level, but mask signal generatingcircuit 104D outputs mask signal Cmask at L level. Consequently, controlcircuit 42E does not invalidate the command received at time T6, butgenerates a corresponding internal control command.

[0193] Referring to FIG. 22, in the example in which the external clockhas a high frequency, when the write command is externally input at timeT1, and when external clock ext.CLK rises at time T6, a delay time bydelay element G18 has not passed yet at this time point, and signalColwidth is at H level. Therefore, access monitoring circuit 108 outputssignal CmaskEN at H level. Accordingly, mask signal generating circuit104D outputs mask signal Cmask at H level, and internal commandgenerating circuit 102 sets signal INTCOM to L level. In other words,control circuit 42E invalidates the command received at time T5.

[0194] When signal Colwidth attains L level at time T7, accessmonitoring circuit 108 sets signal CmaskEN to L level at time T10 in thenext cycle. Therefore, mask signal generating circuit 104D outputs masksignal Cmask at L level, and internal command generating circuit 102outputs signal INTCOM at H level. In other words, control circuit 42Edoes not invalidate the command received at time T9, but generates acorresponding internal control command.

[0195] Here, semiconductor memory device 10E according to Embodiment 6is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 according to Embodiment 1.

[0196] In the above description, the output signal from delay elementG18 simulating the processing time for access to the memory cell arrayhas been used as a signal resetting signal Colwidth to L level.Alternatively, however, a signal indicating a state of the access to thememory cell array may be used.

[0197] As described above, according to semiconductor memory device 10Ein Embodiment 6, a command input in a cycle following the completion ofthe processing for access to the memory cell array is regarded as valid.Therefore, an unnecessary waiting time for the processing is notproduced when semiconductor memory device 10E is used under alow-frequency operation.

[0198] (Embodiment 7)

[0199] Embodiments 1 to 6 have dealt with consecutive inputs of anidentical command. In Embodiment 7, however, a command input later isinvalidated, even if different types of commands are consecutivelyinput.

[0200] A semiconductor memory device 10F in Embodiment 7 includes acontrol circuit 42F instead of control circuit 42 in the configurationof semiconductor memory device 10 shown in FIG. 1. Since otherconfigurations are the same, description thereof will not be repeated.

[0201]FIG. 23 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42F in semiconductor memory device 10F according to Embodiment 7.

[0202] Referring to FIG. 23, control circuit 42F includes a writecommand processing portion 114 and a read command processing portion116. Write command processing portion 114 includes an internal commandgenerating circuit 102C and a mask signal generating circuit 104B. Readcommand processing portion 116 includes an internal command generatingcircuit 110 and a mask signal generating circuit 112.

[0203] Internal command generating circuit 102C includes an NOR gate G45instead of NOR gate G21 in the configuration of internal commandgenerating circuit 102B in Embodiment 3. Internal command generatingcircuit 110 includes an NAND gate G46, inverters G47, G48, latchcircuits G49, G50, and an NOR gate G53. Mask signal generating circuit112 includes a latch circuit G51 and a delay element G52. Here,description for the configuration of mask signal generating circuit 104Bhas already been provided, and will not be repeated.

[0204] NOR gate G45 calculates logical sum of each output signal fromdelay element G52, latch circuit G3, and delay element G20, and outputsa signal obtained by inverting the calculation result as a signal C3W.NOR gate G53 calculates logical sum of each output signal from latchcircuit G49, delay element G20, and delay element G52, and outputs asignal obtained by inverting the calculation result as a signal C3R.Since other configurations in read command processing portion 116 arethe same as those in write command processing portion 114, descriptionthereof will not be provided.

[0205] In control circuit 42F, mask signals CmaskW, CmaskR generatedrespectively by write command processing portion 114 and read commandprocessing portion 116 are used to control inputs in the internalcommand generating circuits in both write command processing portion 114and read command processing portion 116.

[0206]FIG. 24 is an operational waveform diagram illustrating anoperation of control circuit 42F shown in FIG. 23.

[0207] Referring to FIG. 24, when the write command is input at time T1,and when external clock ext.CLK rises at time T2, internal commandgenerating circuit 102C outputs a signal INTCOMW corresponding to thewrite command at H level. When external clock ext.CLK falls at time T4,delay element G20 outputs mask signal CmaskW at H level after aprescribed time.

[0208] When the read command is input at time T6, and when externalclock ext.CLK rises at time T7, internal command generating circuit 110does not activate to H level, a signal INTCOMR corresponding to the readcommand, because mask signal CmaskW has attained H level. In addition,internal command generating circuit 102C sets signal INTCOMW to L level.

[0209] When external clock ext.CLK falls at time T9, delay element G20outputs mask signal CmaskW at L level at time T10 after a prescribedtime. Thereafter, when the read command is input again at time T11, andwhen external clock ext.CLK rises at time T12, internal commandgenerating circuit 110 outputs signal INTCOMR at H level because masksignal CmaskW has attained L level at this time. Control circuit 42Fgenerates an internal control command corresponding to the read command.

[0210] Here, semiconductor memory device 10F according to Embodiment 7is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 in Embodiment 1.

[0211] In addition, instead of mask signals CmaskW, CmaskR, a controlsignal of the memory cell array having a comparable signal timing, forexample, may be used as a signal fixing inputs of latch circuits G4, G50to L level.

[0212] Moreover, in semiconductor memory device 10F described above, theinput of the internal command generating circuit has been blocked. Onthe other hand, as in relations shown in Embodiments 1 to 3, theinternal command generating circuit may be reset, or alternatively, theoutput of the internal command generating circuit may be blocked.

[0213] As described above, according to semiconductor memory device 10Fin Embodiment 7, a command received in a cycle following the receptionof a command is invalidated, even if it is of a different type.Therefore, an overlapped access to the memory cell array is prevented,and data destruction can be avoided.

[0214] (Embodiment 8)

[0215] A semiconductor memory device 10G according to Embodiment 8includes a control circuit 42G instead of control circuit 42 in theconfiguration of semiconductor memory device 10 shown in FIG. 1.

[0216]FIG. 25 is an operational waveform diagram conceptuallyillustrating an operation of control circuit 42G in semiconductor memorydevice 10G according to Embodiment 8.

[0217] Referring to FIG. 25, when semiconductor memory device 10Gsimultaneously receives commands A and B at time T1, the semiconductormemory device activates an internal circuit activation signal Acorresponding to command A having higher priority, while invalidatescommand B. At time T2 in the next cycle, access to the memory cell arrayby internal circuit activation signal A activated at time T1 has notbeen completed. Therefore, semiconductor memory device 10G invalidatesboth commands A and B received from the outside.

[0218] When only command B is input at time T3, semiconductor memorydevice 10G activates an internal circuit activation signal Bcorresponding to command B. Then, even if commands A and B are input attime T4 in the next cycle, semiconductor memory device 10G invalidatesboth commands A and B, because access to the memory cell array byinternal circuit activation signal B activated at time T3 has not beencompleted.

[0219] Thus, when different commands are simultaneously input,semiconductor memory device 10G according to Embodiment 8 activates onlythe internal circuit activation signal corresponding to a command givena priority, and invalidates other commands.

[0220]FIG. 26 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42G in semiconductor memory device 10G according to Embodiment 8.

[0221] Referring to FIG. 26, control circuit 42G includes a writecommand processing portion 114A and a read command processing portion116A. Write command processing portion 114A includes internal commandgenerating circuit 102 and a mask signal generating circuit 104E. Readcommand processing portion 116A includes an internal command generatingcircuit 110A and a mask signal generating circuit 112A.

[0222] Mask signal generating circuit 104E includes an NOR gate G54instead of inverter G10 in the configuration of mask signal generatingcircuit 104 in Embodiment 1. Internal command generating circuit 110Aincludes an NAND gate G46, inverters G47, G48, G55, and latch circuitsG56, G57. Mask signal generating circuit 112A includes latch circuitsG58, G59, an NOR gate G60, and an NAND gate G61. Here, description forthe configuration of internal command generating circuit 102 has alreadybeen provided, and will not be repeated.

[0223] NOR gate G54 calculates logical sum of each output signal oflatch circuits G6, G57, G59, and outputs a signal obtained by invertingthe calculation result to NAND gate G2. As other configurations of masksignal generating circuit 104E are the same as those of mask signalgenerating circuit 104 in Embodiment 1, description thereof will not berepeated.

[0224] NOR gate G60 calculates logical sum of each output signal oflatch circuits G6, G59, and outputs a signal obtained by inverting thecalculation result to NAND gate G61. As other configurations of readcommand processing portion 116A are the same as those of write commandprocessing portion 114A, description thereof will not be provided.

[0225]FIG. 27 is an operational waveform diagram illustrating anoperation of control circuit 42G shown in FIG. 26.

[0226] Referring to FIG. 27, when the read command and the writecommands are simultaneously input at time T1, and when external clockext.CLK rises at time T2, internal command generating circuit 110Aoutputs signal INTCOMR at H level. On the other hand, though internalcommand generating circuit 102 also outputs signal INTCOMW once at Hlevel, internal command generating circuit 102 is immediately reset andinternal command generating circuit 102 immediately sets signal INTCOMWto L level, because mask signal generating circuit 104E outputs masksignal CmaskW at H level, upon receiving signal INTCOMR of H level. Inother words, with regard to the read command and the write commandsimultaneously input at time T1, priority is given to the read command,and the write command is invalidated.

[0227] When the read command is input at time T5 in the next cycle, andwhen external clock ext.CLK rises at time T6, mask signal generatingcircuit 112A outputs mask signal CmaskR at H level. Therefore, controlcircuit 42G invalidates the read command received at time T5.

[0228] Moreover, when the write command is input at time T9 in the nextcycle, and when external clock ext.CLK rises at time T10, mask signalsCmaskW, CmaskR are both set to L level. Therefore, internal commandgenerating circuit 102 outputs signal INTCOMW at H level. That is,control circuit 42G generates an internal control command correspondingto the write command.

[0229] Here, semiconductor memory device 10G according to Embodiment 8is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 in Embodiment 1.

[0230] As described above, according to semiconductor memory device 10Gin Embodiment 8, when different commands are simultaneously received,only a command given a priority is regarded as valid, and other commandsare invalidated. Therefore, an overlapped access to the memory cellarray is prevented, and data destruction can be avoided.

[0231] (Embodiment 9)

[0232] In the semiconductor memory device according to Embodiment 8,when different commands are simultaneously input, one internal controlcommand resets the other internal command generating circuit. Thus,overlapped generation of commands has been avoided.

[0233] A semiconductor memory device according to Embodiment 9 avoidsoverlapped generation of commands by blocking an output of the otherinternal command generating circuit using one internal control command.

[0234] A semiconductor memory device 10H according to Embodiment 9includes a control circuit 42H instead of control circuit 42 in theconfiguration of semiconductor memory device 10 shown in FIG. 1. Sinceother configurations are the same, description thereof will not berepeated.

[0235]FIG. 28 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42H in semiconductor memory device 10H according to Embodiment 9.

[0236] Referring to FIG. 28, control circuit 42H includes a writecommand processing portion 114B instead of write command processingportion 114A in the configuration of control circuit 42G according toEmbodiment 8. Write command processing portion 114B includes an internalcommand generating circuit 102D and a mask signal generating circuit104F. Internal command generating circuit 102D further includes aninverter G63 and an NOR gate G64 in the configuration of internalcommand generating circuit 102 in Embodiment 1. Mask signal generatingcircuit 104F includes an NOR gate G62 instead of NOR gate G54 in theconfiguration of mask signal generating circuit 104E in Embodiment 8.

[0237] Inverter G63 outputs a signal obtained by inverting output signalC3W from latch circuit G4. NOR gate G64 calculates logical sum of outputsignals from latch circuit G57 and inverter G63, and outputs a signalobtained by inverting the calculation result as signal INTCOMW. NOR gateG62 calculates logical sum of output signals from latch circuits G6 andG59, and outputs a signal obtained by inverting the calculation resultto NAND gate G2.

[0238]FIG. 29 is an operational waveform diagram illustrating anoperation of control circuit 42G shown in FIG. 28.

[0239] Referring to FIG. 29, when the read command and the write commandare simultaneously input at time T1, and when external clock ext.CLKrises at time T2, internal command generating circuit 110A outputssignal INTCOMR at H level. On the other hand, though output signal C3Wof latch circuit G4 attains H level in write command processing portion114B, signal INTCOMW attains L level because signal INTCOMR has attainedH level.

[0240] When the read command is input at time T5 in the next cycle, andwhen external clock ext.CLK rises at time T6, mask signal generatingcircuit 112A outputs mask signal CmaskR at H level, and internal commandgenerating circuit 110A outputs signal INTCOMR at L level. In otherwords, control circuit 42H invalidates the read command received at timeT5.

[0241] Further, when the write command is input at time T9 in the nextcycle, and when external clock ext.CLK rises at time T10, mask signalsCmaskW, CmaskR are both set to L level. Therefore, internal commandgenerating circuit 102 outputs signal INTCOMW at H level. In otherwords, control circuit 42H generates an internal control commandcorresponding to the write command.

[0242] Here, semiconductor memory device 10H according to Embodiment 9is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 in Embodiment 1.

[0243] As described above, according to semiconductor memory device 10Hin Embodiment 9 as well, an effect similar to semiconductor memorydevice 10G according to Embodiment 8 can be obtained.

[0244] (Embodiment 10)

[0245] When a semiconductor memory device in Embodiment 10 receivesdifferent commands simultaneously, overlapped generation of commands isavoided by blocking command input of the other internal commandgenerating circuit, using one internal control command.

[0246] A semiconductor memory device 10I according to Embodiment 10includes a control circuit 42I instead of control circuit 42 in theconfiguration of semiconductor memory device 10 shown in FIG. 1. Sinceother configurations are the same, description thereof will not berepeated.

[0247]FIG. 30 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit421 in semiconductor memory device 10I according to Embodiment 10.

[0248] Referring to FIG. 30, control circuit 42I includes an internalcommand generating circuit 102E instead of internal command generatingcircuit 102D in the configuration of control circuit 42H in Embodiment9. Internal command generating circuit 102E includes an inverter G65 andan NOR gate G66 instead of inverter G8 in the configuration of internalcommand generating circuit 102 in Embodiment 1.

[0249] Inverter G65 outputs an inverted signal of an output signal fromNAND gate G46. NOR gate G66 calculates logical multiplication of outputsignals from inverter G65 and NAND gate G1, and outputs a signalobtained by inverting the calculation result to latch circuit G3.

[0250]FIG. 31 is an operational waveform diagram illustrating anoperation of control circuit 42G shown in FIG. 30.

[0251] Referring to FIG. 31, when the read command and the write commandare simultaneously input at time T1, signals C1R, C2R attain H level inread command processing portion 116A. On the other hand, in a writecommand processing portion 114C, though signal C1W, which is an outputsignal of NOR gate G66, once attains H level, it immediately attains Llevel, because the read command has simultaneously been input.Therefore, when external clock ext.CLK rises at time T2, only signalINTCOMR attains H level, and signal INTCOMW does not attain H level. Inother words, control circuit 421 gives priority to the read command, andinvalidates the write command.

[0252] An operation after the read command alone is input at time T5 inthe next cycle is similar to that of control circuit 42H according toEmbodiment 9 shown in FIG. 29.

[0253] Here, semiconductor memory device 10I according to Embodiment 10is also readily expanded to a semiconductor memory device performing the2×k (k>2) bit prefetch operation, in a manner similar to semiconductormemory device 10 in Embodiment 1.

[0254] As described above, according to semiconductor memory device 10Iin Embodiment 10 as well, an effect similar to semiconductor memorydevice 10G in Embodiment 8 can be obtained.

[0255] (Embodiment 11)

[0256] A semiconductor memory device according to Embodiment 11 includesa circuit detecting a simultaneous input of different commands. When thesimultaneous input is detected, all commands are invalidated.

[0257] A semiconductor memory device 10J according to Embodiment 11includes a control circuit 42J instead of control circuit 42 in theconfiguration of semiconductor memory device 10 shown in FIG. 1. Sinceother configurations are the same, description thereof will not berepeated.

[0258]FIG. 32 is an operational waveform diagram conceptuallyillustrating an operation of control circuit 42J in semiconductor memorydevice 10J according to Embodiment 11.

[0259] Referring to FIG. 32, upon receiving commands A and B at time T1,semiconductor memory device 10J detects a simultaneous input of commandsA and B, and does not activate any of internal circuit activationsignals A, B corresponding to commands A, B respectively. Therefore, inresponse to command B input at time T2 in the next cycle, semiconductormemory device 10J activates internal circuit activation signal B.Further, when command A is input at time T3 in the next cycle,semiconductor memory device 10J invalidates command A because it hasactivated internal circuit activation signal B in the previous cycle.

[0260]FIG. 33 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in control circuit42J in semiconductor memory device 10J according to Embodiment 11.

[0261] Referring to FIG. 33, control circuit 42J includes a writecommand processing portion 114D, read command processing portion 116A,and a simultaneous input detecting circuit 118. Write command processingportion 114D includes internal command generating circuit 102 and masksignal generating circuit 104F. Simultaneous input detecting circuit 118includes an AND gate G67, a latch circuit G68, and an inverter G69.Here, description for read command processing portion 116A, internalcommand generating circuit 102, and mask signal generating circuit 104Fhas already been provided, and will not be repeated.

[0262] AND gate G67 outputs a signal obtained by calculating logicalmultiplication of output signals from latch circuits G3, G56. InverterG69 outputs an inverted signal of internal signal /POR. Latch circuitG68 receives internal clock CLK at the clock input. When internal clockCLK attains H level, latch circuit G68 takes in an output signal fromAND gate G67, and outputs the signal as a signal CmaskRW. When internalclock CLK attains L level, latch circuit G68 holds the taken-in signal,and outputs the held signal as signal CmaskRW. In addition, latchcircuit G68 receives an output signal from inverter G69 at the resetinput, and resets the held data when the reset input attains H level.

[0263]FIG. 34 is an operational waveform diagram illustrating anoperation of control circuit 42J shown in FIG. 33.

[0264] Referring to FIG. 34, when the read command and the write commandare simultaneously input at time T1, signals C2R, C2W attain H levelrespectively in read command processing portion 116A and write commandprocessing portion 114D, and an input node of latch circuit G68 attainsH level.

[0265] When external clock ext.CLK rises at time T2, latch circuit G68is activated, and simultaneous input detecting circuit 118 outputssignal CmaskRW at H level. Accordingly, mask signal generating circuits112A, 104F output signals CmaskR, CmaskW at H level respectively.Therefore, signals INTCOMR, INTCOMW corresponding to the read commandand the write command respectively, which are simultaneously input attime T1, both attain L level.

[0266] Next, when only the read command is input at time T5 in the nextcycle, and when external clock ext.CLK rises at time T6, simultaneousinput detecting circuit 118 outputs signal CmaskRW at L level becausesignals C2R, C2W have attained H level and L level respectively. Inaddition, since signals INTCOMR, INTCOMW have both attained L level,mask signal generating circuits 112A, 104F output signals CmaskR, CmaskWat L level respectively. Therefore, at time T6, signal INTCOMR attains Hlevel, and control circuit 42J generates an internal control commandcorresponding to the read command.

[0267] It is to be noted that invalidation of the read command input attime T9 in the next cycle is the same as in the previous embodiments,and description thereof will not be provided.

[0268] In the above description, in invalidating commands in readcommand processing portion 116A and write command processing portion114D, the latch circuit in the internal command generating circuit hasbeen reset by the mask signal. Corresponding to the relation shown inEmbodiments 1 to 3, however, the output or the input of the internalcommand generating circuit may be blocked by the mask signal.

[0269] As described above, according to semiconductor memory device 10Jin Embodiment 11 as well, the internal control commands are notgenerated in an overlapped manner. Therefore, an overlapped access tothe memory cell array can be prevented, and data destruction can beavoided.

[0270] (Embodiment 12)

[0271] In Embodiment 12, an input command holding circuit for generatinga write latency is provided in the write command processing portion.When the internal control command corresponding to the read command isgenerated, data held by the input command holding circuit is invalidatedby that internal control command. Therefore, when the read command isinput after the write command is input, and when the internal controlcommand corresponding to the read command is generated before, orsimultaneously with, the internal control command corresponding to thewrite command, priority is given to the read command, and the writecommand is invalidated. Thus, overlapped access to the memory cell arrayis avoided.

[0272]FIG. 35 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuit42K in a semiconductor memory device 10K according to Embodiment 12.

[0273] Referring to FIG. 35, control circuit 42K includes a writecommand processing portion 114E and read command processing portion116A. Write command processing portion 114E includes an internal commandgenerating circuit 102F and mask signal generating circuit 104F.Internal command generating circuit 102F further includes an inputcommand holding circuit 120 in the configuration of internal commandgenerating circuit 102D in Embodiment 9, and includes an inverter G74and an NAND gate G75 instead of inverter G9. Input command holdingcircuit 120 consists of latch circuits G70 to G73.

[0274] Here, description for the configuration of read commandprocessing portion 116A and mask signal generating circuit 104F hasalready been provided, and will not be repeated.

[0275] Inverter G74 outputs an inverted signal of signal INTCOMR. NANDgate G75 calculates logical multiplication of an output signal frominverter G74 and internal signal /POR, and outputs a signal obtained byinverting the calculation result. Latch circuits G70, G72 operate uponreceiving internal clock /CLK at the clock inputs, while latch circuitsG71, G73 operate upon receiving internal clock CLK at the clock inputs.In addition, latch circuits G70-G73 receive an output signal from NANDgate G75 at the reset inputs, and reset the held data when the resetinput is at H level.

[0276] Here, the reason why inverter G63 and NOR gate G64 are providedin an output stage of internal command generating circuit 102F, eventhough input command holding circuit 120 is reset by signal INTCOMR, isbecause simultaneous attainment of H level of signals INTCOMR, INTCOMWshould be avoided.

[0277]FIG. 36 is an operational waveform diagram illustrating anoperation of control circuit 42K shown in FIG. 35.

[0278] Referring to FIG. 36, when the write command is input at time T1,and when external clock ext.CLK rises at time T2, signal C3W is set to Hlevel, and input information of the write command is held in inputcommand holding circuit 120. Here, signal INTCOMW does not attain Hlevel until WL has expired (here, an example in which WL=2.0 is shown).

[0279] When the read command is input at time T5 in the next cycle, andwhen external clock ext.CLK rises at time T6, in write commandprocessing portion 114E, data is shifted within input command holdingcircuit 120, and a signal C4W attains H level. On the other hand, inread command processing portion 116A, signal INTCOMR attains H level.Then, an output signal of NAND gate G75 is switched to H level, andlatch circuits G70-G73 constituting input command holding circuit 120are reset. In other words, control circuit 42K invalidates the writecommand in response to generation of an internal control commandcorresponding to the read command.

[0280] As described above, an example in which WL=2.0 has been shown inthe present embodiment. On the other hand, by modifying as appropriatethe number of stages of the latch circuit contained in the input commandholding circuit, the semiconductor memory device according to thepresent embodiment can readily be expanded to an example in which WL orAL is varied. In addition, the input command holding circuit may beprovided in the read command processing portion as required.

[0281] As described above, according to semiconductor memory device 10Kin Embodiment 12, an internal control command corresponding to onecommand is used to reset the other input command holding circuit.Therefore, overlapped access to the memory cell array can be avoided,even if WL or AL is present.

[0282] (Embodiment 13)

[0283] In Embodiment 12, the internal control command corresponding toone command has been used to reset the other input command holdingcircuit. In Embodiment 13, an internal control command corresponding toone command is used to block the output of the other input commandholding circuit. In doing so, when the internal control commandcorresponding to one command is generated, generation of an internalcontrol command corresponding to the other command can be blocked.

[0284]FIG. 37 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuit42L in a semiconductor memory device 10L according to Embodiment 13.

[0285] Referring to FIG. 37, control circuit 42L includes a writecommand processing portion 114F and read command processing portion116A. Write command processing portion 114F includes an internal commandgenerating circuit 102G and mask signal generating circuit 104F.Internal command generating circuit 102G further includes an inputcommand holding circuit 120A and an inverter G76 in the configuration ofinternal command generating circuit 102D in Embodiment 9. Input commandholding circuit 120A further includes AND gates G77, G78 in theconfiguration of internal command holding circuit 120 in Embodiment 12,and receives the output signal from inverter G9 instead of an outputsignal from NAND gate G75 at the reset inputs of latch circuits G70-G73.

[0286] Here, description for the configuration of read commandprocessing portion 116A and mask signal generating circuit 104F hasalready been provided, and will not be repeated.

[0287] Inverter G76 outputs an inverted signal of signal INTCOMR. ANDgate G77 outputs to latch circuit G72, a signal obtained by calculatinglogical multiplication of output signals from latch circuit G71 andinverter G76. AND gate G78 outputs to latch circuit G3, a signalobtained by calculating logical multiplication of output signals fromlatch circuit G73 and inverter G76.

[0288]FIG. 38 is an operational waveform diagram illustrating anoperation of control circuit 42L shown in FIG. 37.

[0289] Referring to FIG. 38, the operational waveform diagram of controlcircuit 42L is similar to that of control circuit 42K in Embodiment 12.In other words, when the write command is input at time T1, and when theread command is input at time T5 in the next cycle, with the rise ofexternal clock ext.CLK at time T6, signal INTCOMR attains H level.Accordingly, an output signal of inverter G76 in write commandprocessing portion 114F attains L level. Therefore, output signals ofAND gates G77, G78 are fixed to L level, and the write command isinvalidated.

[0290] In Embodiment 13 as well, an example in which WL=2.0 has beenshown. As described in Embodiment 12, however, by modifying asappropriate the number of stages of the latch circuit contained in theinput command holding circuit, the semiconductor memory device accordingto the present embodiment can readily be expanded to an example where WLor AL is varied. In addition, the input command holding circuit may beprovided in the read command processing portion as required.

[0291] As described above, according to semiconductor memory device 10Lin Embodiment 13 as well, an effect similar to semiconductor memorydevice 10K in Embodiment 12 can be obtained.

[0292] (Embodiment 14)

[0293] In Embodiment 13, the internal control command corresponding toone command has been used to block the output of the other input commandholding circuit. In Embodiment 14, one command is used to block theinput of the other input command holding circuit.

[0294]FIG. 39 is a circuit diagram showing a configuration of a portioninvolved in generating an internal control command in a control circuit42M in a semiconductor memory device 10M according to Embodiment 14.

[0295] Referring to FIG. 39, control circuit 42M includes a writecommand processing portion 114G and read command processing portion116A. Write command processing portion 114G includes an internal commandgenerating circuit 102H and mask signal generating circuit 104F.Internal command generating circuit 102H further includes an inputcommand holding circuit 120B in the configuration of input commandgenerating circuit 102D in Embodiment 9, and includes an inverter G79and an NOR gate G80 instead of inverter G8. Input command holdingcircuit 120B further includes an AND gate G81 in the configuration ofinput command holding circuit 120 in Embodiment 12, and receives theoutput signal from inverter G9 instead of the output signal from NANDgate G75 at the reset inputs of latch circuits G70-G73.

[0296] Here, description for the configuration of read commandprocessing portion 116A and mask signal generating circuit 104F hasalready been provided, and will not be repeated.

[0297] Inverter G79 outputs an inverted signal of the output signal fromNAND gate G46. NOR gate G80 calculates logical multiplication of outputsignals from NAND gate G1 and inverter G79, and outputs a signalobtained by inverting the calculation result to latch circuit G70. ANDgate G81 outputs to latch circuit G72, a signal obtained by calculatinglogical multiplication of output signals from latch circuit G71 and NANDgate G46.

[0298]FIG. 40 is an operational waveform diagram illustrating anoperation of control circuit 42M shown in FIG. 39.

[0299] Referring to FIG. 40, the operational waveform diagram of controlcircuit 42M is similar to that of control circuit 42K in Embodiment 12.In other words, when the write command is input at time T1, and when theread command is input at time T5 in the next cycle, signals C1R, C2Rattain H level in read command processing portion 116A, while signal C3Wattains L level in write command processing portion 114G.

[0300] Then, when external clock ext.CLK rises at time T6, in readcommand processing portion 116A, signal INTCOMR attains H level, and aninternal control command corresponding to the read command is generated.On the other hand, in write command processing portion 114G, the writecommand held by input command holding circuit 120B is invalidated,because signals C1W, C3W have attained L level.

[0301] Here, if signal C4W has already attained H level when controlcircuit 42M receives the read command, that is, if timings of generationof the internal control commands corresponding to the read command andthe write command coincide, signal INTCOMW does not attain H level, butsignal INTCOMR is given priority to attain H level. This is becauseinverter G63 and NOR gate G64 are provided in the output stage of signalINTCOMW.

[0302] In Embodiment 14 as well, an example in which WL=2.0 has beenshown. As described in Embodiment 12, however, by modifying asappropriate the number of stages of the latch circuit contained in theinput command holding circuit, the semiconductor memory device accordingto the present embodiment can readily be expanded to an example where WLor AL is varied. In addition, the input command holding circuit may beprovided in the read command processing portion as required.

[0303] As described above, according to semiconductor memory device 10Min Embodiment 14 as well, an effect similar to semiconductor memorydevice 10K in Embodiment 12 can be obtained.

[0304] Although the present invention has been described and illustratedin detail, it is dearly understood that the same is by way ofillustration and example only and is not to be taken by way ofimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor memory device communicating datawith outside in synchronization with a rise and a fall of an externalclock, comprising: a plurality of memory cells storing data; an internalcircuit inputting/outputting data to/from said plurality of memorycells; and a control circuit controlling an operation of said internalcircuit in an operation unit being consecutive, multiple cycles of saidexternal clock; wherein said control circuit includes an internalcommand generating circuit generating an internal control command toinstruct an operation of said internal circuit based on an externallyinput control command, said internal command generating circuit carriesout one of first and second processings, upon receiving a plurality ofcontrol commands corresponding to a plurality of internal controlcommands generated within said multiple cycles, in said firstprocessing, an internal control command corresponding to any one of saidplurality of control commands is generated, while at least one, othercontrol command is invalidated, and in said second processing, saidplurality of control commands are all invalidated.
 2. The semiconductormemory device according to claim 1, wherein said internal commandgenerating circuit, in said first processing, generates an internalcontrol command corresponding to a control command received in a firstplace among said plurality of control commands, and invalidates at leastone, the other control command.
 3. The semiconductor memory deviceaccording to claim 2, wherein said control circuit further includes asignal generating circuit generating a first signal, and said internalcommand generating circuit receives said first signal, and invalidates acontrol command received from outside when said first signal isactivated.
 4. The semiconductor memory device according to claim 3,wherein said signal generating circuit activates said first signal froma time point when said internal control command corresponding to saidcontrol command received in the first place is generated until a timepoint when said multiple cycles expire.
 5. The semiconductor memorydevice according to claim 3, wherein said control circuit furtherincludes another signal generating circuit generating a second signal insynchronization with generation of said first signal, and said signalgenerating circuit receives said second signal, and inactivates saidfirst signal when said second signal is inactivated.
 6. Thesemiconductor memory device according to claim 5, wherein said anothersignal generating circuit activates said second signal from a time pointwhen said internal control command corresponding to said control commandreceived in the first place is generated until a time point when accessto said plurality of memory cells by said internal circuit is completed.7. The semiconductor memory device according to claim 1, wherein saidinternal command generating circuit, in said first processing,invalidates at least one, the other control command by using an internalcontrol command corresponding to a control command given a priority inaccordance with a prescribed priority order.
 8. The semiconductor memorydevice according to claim 7, wherein said prescribed priority order isdetermined in accordance with a type of said plurality of controlcommands.
 9. The semiconductor memory device according to claim 7,wherein said prescribed priority order is determined in accordance withan order of generation of a plurality of internal control commandscorresponding to said plurality of control commands.
 10. Thesemiconductor memory device according to claim 1, wherein when a cancelcommand canceling a processing requested by an internal control commandgenerated through said first processing is input from outside to cancelsaid processing, said internal command generating circuit carries outone of said first and second processings with respect to said pluralityof control commands except for a control command corresponding to theinternal control command corresponding to said cancelled processing. 11.The semiconductor memory device according to claim 1, wherein when acancel command canceling a processing requested by an internal controlcommand generated through said first processing is input from outside,said control circuit invalidates said cancel command.
 12. Thesemiconductor memory device according to claim 1, wherein in saidinternal command generating circuit, an internal state is reset based onthe internal control command generated in said first processing, andsaid internal command generating circuit invalidates at least one, theother control command held inside.
 13. The semiconductor memory deviceaccording to claim 1, wherein said internal command generating circuitprevents an output of an internal control command corresponding to atleast one, said other control command in said multiple cycles based onthe internal control command generated in said first processing.
 14. Thesemiconductor memory device according to claim 1, wherein said internalcommand generating circuit prevents an input of at least one, said othercontrol command in said multiple cycles based on the internal controlcommand generated in said first processing.
 15. The semiconductor memorydevice according to claim 1, wherein said control circuit furtherincludes a signal generating circuit generating an invalidating signalfor invalidating at least one, said other control command based on saidinternal control command, and said internal command generating circuitreceives said invalidating signal, and invalidates a control commandreceived from outside in said first processing when said invalidatingsignal is activated.
 16. The semiconductor memory device according toclaim 1, wherein said control circuit further includes a detectingcircuit detecting simultaneous generation of said internal controlcommand, and said internal command generating circuit carries out saidsecond processing based on a detected result of said detecting circuit.